Modern Multi-Band Radio Frequency (RF) systems, such as “4G” Cellular systems, are running into fundamental limitations of previous-generation systems, which requires system designers to fundamentally change the structure of the underlying system circuitry. Previous-generation systems are constructed, for the most part, using classic RF system techniques, such as analog mixers and separate analog Base Band and RF filters. Newer systems are transitioning to make use of two new classes of circuits: RF Digital/Analog Converters (RF DACs) and RF Analog/Digital Converters (RF ADCs). These RF converters push the Analog/Digital boundary much closer to the antenna, increasing the available RF bandwidth available and allowing for much more flexibility in the system, by pushing functionality that was previously in the analog circuits into digital circuits or even into software. This latter functionality is often called “Software Defined Radio”, or SDR, and is seen as the ultimate in flexibility, allowing major functional changes of the RF system through a software or firmware download.
In order to understand an RF DAC, it is helpful to understand the fundamentals of a conventional RF transmit signal chain. FIG. 1 shows a representative previous-generation signal chain; not all previous-generation signal chains would contain all the elements of FIG. 1 and there may be variants, however the differences can be readily understood.
The signal chain accepts Base Band (BB) In-Phase/Quadrature (I/Q) sample data from the BBMedia Access Controller (MAC) through a Digital Interface 100. The I/Q data (that is, the I-data and the Q-data) is interpolated to a higher sample rate through an interpolator 110, and then is optionally modulated to adjust the center frequency to an Intermediate Frequency (IF) through a Digital Quadrature Modulator (DQM, 120). The interpolated and modulated I and Q digital signals are fed through two DACs (140) to produce an analog signal, which is filtered by two matched BB/IF filters (150). The filtered signal data is mixed using an Analog Quadrature Modulator (AQM, 160) with a Local Oscillator (LO) clock to produce an RF output. An RF Filter (170) filters the AQM output before amplifying it using a Power Amplifier (PA, 180) to produce the signal that will be actually transmitted by the antenna (190).
In addition to the circuit elements, FIG. 1 has two clocks. The first, the Base Band Clock (often referred to as SYSCLK), determines the sample data rate at the Digital Interface, and is also used to clock the Interpolator, DQM, and DACs. For convenience, FIG. 1 shows all blocks running from the same clock, SYSCLK, however depending upon the details of the actual system, some other clock SYSCLK·M (M being an integer) or SYSCLK/M might actually be used in a particular block. Powers of 2 (i.e. 2N) are commonly used for M because they allow for ready use of efficient Digital Signal Processor (DSP) filter techniques, but other factors may also be used. The second clock, the Local Oscillator clock (LO) drives the AQM and sets the center frequency of the transmitted RF output. The structure and operation of the AQM are well known to those skilled in the art.
One key difficulty in the design of a conventional RF transmit signal chain comes in the relationship between the two clock frequencies. SYSCLK is, of necessity, a standard fixed frequency; in cellular base stations, this is typically a power of 2 multiple of 122.88 MHz or 153.6 MHz, however other frequencies may be chosen depending upon the system design. LO is typically the center frequency of the desired RF signal band or is slightly offset from it and, depending upon the particular frequency band being used, can vary widely from system to system. Because these two frequencies (SYSCLK and LO) are set by two different constraints, they are often completely unrelated to each other, which in turn creates challenges in frequency planning.
Frequency planning essentially boils down to determining a pair of frequencies for SYSCLK and LO, together with an IF that when taken together create an interference-free range of frequencies for a desired RF band. Due to a number of practical circuit issues, harmonics of SYSCLK and LO will often mix together and create spurs, and if one of these spurs is in the desired RF band, performance of the RF system will be degraded. When desired RF bands are narrow, both as a fraction of the available BB/IF bandwidth and the LO frequency, frequency planning can be straightforward. However in modern RF systems, especially those that make use of Digital Pre-Distortion (DPD), the required RF bandwidths are becoming much wider relative both to the BB/IF bandwidth and the LO frequency and, as a result, the frequency planning challenges are becoming harder.
Another key difficulty in the design of a conventional RF transmit signal chain comes from the BB/IF filters. In these systems, the BB/IF filters are the point where the signals cross from one clock domain (SYSCLK) into the other (LO), therefore these filters, which smooth the discrete output signal generated by the DAC to make them appear to be continuous, often must have comparatively large attenuation at multiples of SYSCLK in order to attenuate images and to minimize any coupling between the two clock domains that could create spurs at the output. This requirement in turn requires that the BB/IF filters be of comparatively high order, which often creates significant design challenges. Some of the challenges relate to the cost (bill of materials), non-idealities, and filter design time. A high order differential LC filter uses multiple high-precision components, which are expensive and occupy a large printed circuit board area. Amplitude and/or phase mismatch between the BB/IF filters introduce nonlinearities that degrade system performance. In addition, it is difficult to provide a flat filter response over a wide bandwidth. Any ripple or roll-off also degrades system response. Lastly, it is common for these radio systems to support different radio bands. It follows that the BB/IF filters will therefore need to be different for each radio band. This scales the design time as well as the number of components needed to realize the different BB/IF filters. This greatly complicates the radio system.
In early designs, IF's could be relatively large, and the signals going into the AQM were radically asymmetric in frequency. As a result, the BB/IF filters were truly bandpass IF filters, and every frequency band required a different filter design, which created additional challenges for RF system vendors in designing and maintaining many band-specific designs. As RF bandwidths increased, there was a push to increase the available bandwidth from the BB portion of the system, which in turn resulted in a push to Low-IF or Zero-IF (ZIF) systems. This modification reduced the need for band-specific designs, making these filters truly BB filters, however created an increased potential for additional effects due to mismatch between the I and Q filters. These effects, such as I/Q Impairment (IQI) and LO FeedThru (LOFT), become challenges that the system designer needs to deal with, either by increased production costs to tune the filters or, more commonly, by the addition of new blocks to measure these effects and correct for them in the digital domain.
RF DAC Transmit Signal Chains
Many modern RF transmit signal chains are moving to RF DACs, essentially DACs whose outputs are already modulated, in order to simplify the frequency planning challenges and remove the BB/IF filters, while at the same time increasing the available RF bandwidth at the antenna. An example of such a signal chain is shown in FIG. 2. In FIG. 2, and in all successive figures, an attempt has been made to use similar identification numbers to identify similar blocks. As with FIG. 1, BB I/Q samples are received from a MAC through the Digital Interface 100. These signals are interpolated to a higher sample rate with the interpolator 210, then modulated by the DQM 220, and converted to an analog signal by the RF DAC 240. The modulated signal is in turn filtered by an RF filer 270 and is then amplified by the PA 180 for transmission via the antenna 190.
For convenience, FIG. 2 shows all blocks driven by a single clock, SYSCLK, however as with FIG. 1, the various blocks are likely driven by multiple different clocks, all integer multiples of SYSCLK. In particular, because the RF DAC 240 is running at a significantly higher sample rate (Fs) than the I/Q DACs 140, the interpolator 210 and DQM 220 are similarly going to have significantly higher output sample rates than the interpolator 110 and DQM 120.
By performing the modulation in the digital domain, using DQM 220 instead of AQM 160, and by removing the BB/IF filters 150, all system issues caused by analog imperfections or mismatch have been removed. The challenges of maintaining multiple complex band-specific filter designs have also been removed, and furthermore because there is only a single clock domain in the system, the frequency planning challenges caused by having two clock domains are also gone, allowing greater freedom to increase RF bandwidths to accommodate modern system requirements.
Finally, because the characteristics at the output are completely determined by digital circuitry, system designers are free to envision new and different ways of constructing the systems, bringing the ability to increase system modularity and/or move to the ideal of having a Software-Defined Radio (SDR).
RF DAC Transmit Signal Chain Challenges
While the RF DAC Transmit Signal Chain of FIG. 2 has significant advantages over the conventional signal chain of FIG. 1, a system designer has several new challenges to overcome.
The first two RF DAC challenges are the so-called “sin(x)/x” or “sinc” response inherent to DAC designs and the images that come from the DAC discrete-time output. The output from a DAC over time is not a smooth continuous signal; it instead has a discrete-time staircase shape, sometimes called a “zero order hold”. In turn, the zero-order hold has a frequency response that is given by the equation sin(x)/x, which is plotted in FIG. 3. The vertical axis of this figure is the frequency response in dB, while the horizontal axis is the output frequency as a fraction of Fs, which is the DAC sample rate or the DAC sampling frequency. As is shown, the sin(x)/x response creates a frequency response notch at Fs, meaning that all signal energy at the sample rate is completely attenuated. There are additional notches at Fs·2, Fs·3, and so on, however these are not shown. Also shown in FIG. 3 are the first and second “Nyquist Zones”, which are frequency bands whose width is equal to the Nyquist Frequency Fs/2. Nyquist Zone 1 is a frequency band that extends from DC to Fs/2 and Nyquist Zone 2 is a frequency band that extends from Fs/2 to Fs. There are additional Nyquist Zones that extend beyond Fs that are not shown; for example Nyquist Zone 3 extends from Fs to Fs·3/2, while Nyquist Zone 4 extends from Fs·3/2 to Fs·2. Because the DAC output is a discrete-time signal, output signals that are centered on DC have images centered on Fs, Fs·2, Fs·3, and so on. Therefore, any signal energy in Nyquist Zone 1 will have an image (mirrored at Fs/2) in Nyquist Zone 2 and vice versa. There are additional images in all other Nyquist Zones, but for the purposes of this discussion this is not important.
Examining the sin(x)/x frequency response in FIG. 3, the challenges it causes are clear. FIG. 4 shows the frequency response of two representative RF signals 401 and 402 transmitted in Nyquist Zone 1. For example, if an RF system designer wished to use the RF signal 401, centered around Fs·0.125, there would only be approximately 1 dB of attenuation at the center frequency of the RF signal 401 due to the sin(x)/x response, which for most systems is relatively easy to accommodate. However, if the RF designer wished to use the RF signal 402 centered around Fs·0.375, there would be approximately 2 dB of attenuation at the center frequency of the RF signal 402, meaning that approximately 20% of the signal power is lost due to the sin(x)/x response. Additionally, as is shown at FIG. 4, sin(x)/x roll-off across the bands of the RF signals 401 and 402 can be significant, which means that the RF designer likely must compensate for this (most likely by using digital techniques) to create a flatter response over frequency.
Additionally, the images from these two RF signals 401 and 402 create challenges to the RF system designer. FIG. 4 shows the images 411 and 412 (in Nyquist Zone 2) of the RF signals 401 and 402 (in Nyquist Zone 1). Images 411 (centered at Fs·0.875) and 412 (centered at Fs·0.625) are both in Nyquist Zone 2. Image 411 is approximately 16 dB attenuated relative to frequency response of the RF signal 401, and is furthermore spaced relatively far away. As a result, the required RF filter 270 (shown in FIG. 2) required to reject the image 411 is relatively straight forward to construct. However, to use such a system for an RF center frequency of 4 GHz would require a sample frequency Fs of 32 Gsps (Giga samples per second), which is a significant challenge in and of itself. For comparison, if the RF signal 402 were to have a center frequency of 4 GHz, the required Fs would be a comparatively modest 10.67 Gsps. However, the image 412, is much closer to the RF signal 402 than the image 411 is to the RF signal 401, and is also only approximately 4 dB lower than RF signal 402. In general the larger an image is or the closer it is to the signal, the harder it is to filter out, which in turn requires a higher complexity (and cost) RF filter 270, which means that there is a direct engineering tradeoff between DAC sample rate and RF filter cost.
FIG. 5 shows an alternate approach, with RF signal 503 transmitted in Nyquist Zone 2 (centered at Fs·0.75) and its image 513 in Nyquist Zone 1 (centered at Fs·0.25). In this scenario, the image 513 is approximately 9 dB higher than the RF signal 503, however the signal-to-image spacing is significantly greater than that of RF signal 402 to image 412 (FIG. 4), which simplifies the design of the RF filter 270. For operation at 4 GHz, RF signal 503 requires a sample rate of only 5.33 Gsps, which is much lower than that required for either RF signals 401 or 402 of FIG. 4; however the DAC sin(x)/x response has attenuated the RF signal 503 by approximately 10 dB, meaning that approximately 90% of the signal power has been lost due to the DACs sin(x)/x response.
Another challenge that RF DACs pose for the RF system designer is again frequency planning. Like the two-clock frequency planning challenges of FIG. 1, the frequency planning challenges of a one-clock system, like FIG. 2, arise from the fixed-frequency BB clock SYSCLK. However unlike FIG. 1, where SYSCLK and LO are unrelated, in FIG. 2 the DAC's Fs (sample frequency) is a multiple of SYSCLK which means that the system designer must choose an appropriate multiple in order to make the challenges from sin(x)/x and images manageable. For example, an RF band centered around 4 GHz with a SYSCLK of 122.88 MHz and a signal placement similar to RF signal 402 (FIG. 4) requires a sample frequency Fs approximately 10.67 Gsps, or approximately SYSCLK·83. A multiple of 83 is challenging to accomplish; it is more likely that the system designer will chose a power of 2 (i.e. 64 or 128) or (much less likely) a power of 2 multiplied by a 3 or by 5 (i.e. 80 or 96). The further the chosen multiple is away from the ideal multiple, the less ideal the resulting system is. If the multiple (and therefore Fs) is too low, the closer the RF signal will be to the frequency response notch at Fs/2, and in fact, in this scenario, a multiple of 64 will actually result in the signal band ending up in Nyquist Zone 2. If the multiple (and therefore Fs) is too high, the RF DAC must run at a higher frequency.
One approach to operating in the Nyquist zone 2 that has been used in several recent designs makes use of what is called “Mix Mode” or “RF Mode”. In this approach, the RF DAC is configured to produce an IF signal, and then the DAC inverts its output during the second half of every sample, usually using a slight variation on the Differential Quad Switching (DQS) technique. Referring now to FIG. 6, in one step this translates an IF signal 604 that was originally in Nyquist Zone 1 into an RF signal 604A in Nyquist Zone 2 and an image 614A of in Nyquist Zone 3 with only approximately 3 dB reduction in signal level due to sin(x)/x effects. While this technique is quite effective, it is only effective in Nyquist Zone 2 and the frequency spacing between RF signal 604A and image 614A must be considered (in Nyquist Zone 3) which reduces its utility somewhat.
Yet another shortcoming of RF DAC systems is the required DAC sample rate, Fs, and the resulting power that it dissipates. Simply put, the higher Fs is, the more complex the design of the RF DAC is and the more power it dissipates. Almost all RF DAC systems in use today are segmented CMOS current-mode designs, using arrays of matched current sources (each current source representing a DAC Least Significant Bit, or LSB) coupled to current steering structures (one per current source) that produce their outputs as differential currents. Most designs make use of Differential Quad Switching (DQS) approaches in order to minimize effects on the output caused by rise and fall mismatches. In CMOS logic, dynamic power increases linearly both with frequency and with the total capacitance being driven. The DQS structures are driven by arrays of digital latches, and delay mismatch between these latches appears as gain mismatch between individual LSB elements. In many modern RF DAC designs, LSB gain mismatch due to latch delay mismatches is the dominant source of mismatch, and in order to reduce this the devices that make up the latches are physically large, which increases the total capacitance being driven and therefore increases the power. As Fs increases, power increases, but additionally the required latch mismatch is reduced, so the devices are made even larger, with the end result that dynamic power in the latch array tends to increase at a higher rate than just with Fs. For a 4 GHz LO, this means that Fs=10.67 Gsps required for RF signal 402 (FIG. 4) will dissipate much less power than the Fs=32 Gsps required for RF signal 401 (FIG. 4), and Fs=5.67 Gsps required for RF signal 503 (FIG. 5) will dissipate even less. In fact, depending upon the technology the RF DAC is implemented in (Silicon CMOS, BiCMOS, or bipolar or exotic process such as SiGe, GaAs, or InP) and the minimum feature size (180 nm, 130 nm, 90 nm, 65 nm, 40 nm, 28 nm, 20 nm, or smaller) it may not even be possible to implement the chosen Fs without moving to a totally different architecture, which may increase power even more.
Taken together, the DAC sin(x)/x response, the DAC images, frequency planning, and power dissipation mean that the RF DAC transmit signal chain designer has a large design space to choose from, trading off RF DAC sample rate and architecture, RF filter complexity, and digital complexity all in order to achieve the required target specifications while overcoming all these challenges. If the RF system is intended to cover a wide range of LOs, as in a modern 4G system where LO's can potentially cover a continuous range approximately 400 MHz to 4 GHz, all the design space is much larger, because now the system must either be designed to accommodate the worst-case combination of conditions or the system must be reconfigured depending upon the LO frequency in order to remain efficient.
To date, available RF DAC solutions have not simultaneously provided a wide LO frequency range, high RF bandwidths, simple frequency planning, and high power efficiency.
Therefore, improvements in RF DACs are desirable.